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  4. 6.Configuration Files Guide

6.Configuration Files Guide

When USB2.0 Camera Shield Rev.E is used with different cameras or different modes of the same camera, the upper computer needs to load the different configuration files.

USB2.0 Camera Shield Rev.E config file 1
USB2.0 Camera Shield Rev.E config file 1.2

USB2.0 Camera Shield Rev.E config files is here:


The following configuration file will be used as an example to illustrate a detailed description of the contents of the configuration file so that you can modify it to suit your needs.

USB2.0 Camera Shield Rev.E config file 2

1.About Comments

The lines starting with “;” and “//” are all comments.

Large comments at the beginning of the configuration file are a description of the display mode, camera address, and other configuration methods.

USB2.0 Camera Shield Rev.E config file 2.1

Comments are sometimes added after the camera register configuration to explain the register function.

USB2.0 Camera Shield Rev.E config file 2.1.1

2.Display Mode and Camera Address Configuration

Lines starting with [camera parameter] are for configuring the display mode and camera address.

USB2.0 Camera Shield Rev.E config file 2.2



CFG_MODE  = 0:Parameters can be modified in the upper computer software interface.

CFG_MODE  = 1:Parameters can not be modified in the upper computer software interface.

2.2 TYPE


TYPE is used to mark the camera model for easy viewing.


NOTE: TYPE is just a comment, it doesn’t matter if you write it wrong.

2.3 SIZE


If it does not match the actual output resolution of the camera, a Bad frame received error will be displayed.


Click 【Tools】-【Data Info】 to view the MIPI camera resolution message from the hardware CPLD in real time.





  • MIPI RAW8 mode: camera output is 8bit, BIT_WIDTH is set to 8bit.
  • MIPI RAW10 mode: camera output is 10bit. Because the upper computer cannot parse RAW10 at the moment, the CPLD hardware on USB2.0 Camera Shield Rev. E is throwing away the lower two bits of 10bit and turning them into 8bit before uploading, so BIT_WIDTH is also set to 8bit.
  • DVP mode: DVP input is 12bit. If BIT_WIDTH is set to 8, the high 8 bits of 12 bits are taken; if BIT_WIDTH is set to 12, it is filled into 16 bits of data (high 4 bits are filled with 0) and then uploaded, while the bit[7] of CPLD register 0x01 should be set to 1. At this time, the data bit width is doubled, so the bandwidth is also doubled, which may lead to the bandwidth exceeding the limit of USB2 (about 40MB/s) and needs to be processed by frame down.

Example for BIT_WIDTH = 12




FORMAT = 0, 2 means the order of GB in the four arrangements of RAW, or you can load the configuration file and then switch to adjust it in the lower right corner of the upper computer.




I2C_MODE = 2 means the camera I2C operating mode is 16-bit address, 8-bit data.
I2C_ADDR = 0x6C means that the imager device address is 0x6C.

The I2C operating mode and device address of the imager should be referred to the imager manual or other reference materials.


3.USB Firmware and CPLD Configuration

7.3 USB and CPLD Configuration1
7.3 USB and CPLD Configuration2

Only the configuration in [board parameter] and [board parameter][dev2] are valid for the USB2.0 Camera Shield Rev.E.

3.1 USB Firmware Configuration

VRCMD = 0xF6, 0x0000, 0x0000, 3, 0x03, 0x04, 0x0C are USB2.0 firmware configurations, which generally do not need to be changed.

3.2 CPLD Configuration

On the USB2.0 Camera Shield Rev.E has a CPLD for camera data processing.

7.3 USB and CPLD Configuration3
7.3 USB and CPLD Configuration4

The CPLD can achieve different functions through register configuration.

Register Table

register address

register typeUC-391 Rev.E (USB 2.0)
0x00read-onlybit[7:0]: CPLD version number
UC-391 Rev.E: 0x25
0x01read-writebit[7]: DVP Camera 8/16bit 
0:8bit; 1:16bit
bit[5]: DVP Camera pclk polarity 
0: normal; 1:inverse 
bit[4]: ircut 

0: on; 1: off 

bit[3]: DVP Camera standby 

0: normal; 1: standby

bit[2]: DVP Camera rst_n 

0: rst; 1: normal 

bit[1]: MIPI Camera standby 

0: normal; 1: standby

bit[0]: MIPI Camera rst_n 

0: rst; 1: normal
0x02read-writebit[8]: Select the external trigger connected to CPLD by DVP camera as input or output of CPLD 
0: CPLD input; 1: CPLD output 

bit[4]: Choose whether the internal simulative data a counter or a color bar 
0: color bar; 1: counter

bit[2]: simulative data/camera data 
0: camera data; 1: simulative data 

bit[0]: DVP Camera vsyn polarity 
0: normal; 1: inverse
0x03read-writebit[7]: cpld reset 
0: normal; 1: reset Set it to 1 and then set it back to 0

bit[6]: Pause Camera Data Input 
0: normal; 1: pause

bit[5]: Single shot( Not valid until bit [6] is 1)
0: wait; 1: Start a single shot Set it to 1 and then set it back to 0

bit[7:0]: Frame skipping function. Because the number of input frames may be faster than the bandwidth of USB 2.0, the number of uploaded frames can be reduced by frame hopping. 



Normally, for each N frame, take M frames. 

0x00, No frame skipping 

0x01, Skip 1 frame.That’s1/2(To be compatible with Rev.C.) 

0x11, No frame skipping 

0x12, 1/2 

0x13, 1/3

0x1F, 1/15

0x05read-onlybit[7:0], CPLD version year 
For example decimal 19, the upper machine-readable register value will be added 2000, indicating 2019
0x06read-onlybit[7:0]: CPLD version month 
For example decimal 08, for August
0x07read-onlybit[7:0]: CPLD version date 
For example decimal 03, for 3
0x08read-writebit[7]: Is data uploaded to USB 
0: normal; 1: Stop uploading 

bit[0], Upper computer clears finish ID of single-shot mode 
0: Not clear up; 1: clear up 
Set it to 1 and then set it back to 0
0x09read-onlybit[0]: finish ID of single-shot mode 
0: unfinished; 1: finished
0x0Aread-writebit[1:0]: Data Bit Selection of DVP Camera 
DVP Camera, The input data is 12 bits 
【8-bit mode】 
0: dvp_data[11:4] 
1: dvp_data[9:2] 
2: dvp_data[7:0] 
【16-bit mode】 
0: {4’d0, dvp_data[11:0]} 
1: {6’d0, dvp_data[9:0]}
0x0Cread-writebit[7]: Camera Selection 
0: DVP Camera; 1: MIPI Camera 
bit[4]: MIPI RAW format 
0: raw8; 1: raw10
bit[1:0]: MIPI channel 
0:1Lane; 1:2Lane; 2:4Lane
0x0Dread-writeMIPI, Image resolution, column, High 8 bits
0x0Eread-writeMIPI, Image resolution, column, Low 8 bits
0x0Fread-writeMIPI, Image resolution, row, High 8 bits
0x10read-writeMIPI, Image resolution, row, Low 8 bits
0x11read-writebit[5:4]: ECC check mode 
3: {DI, WC_I, WC_H} 
2: {DI, WC_H, WC_I} 
1: {WC_I, WC_H, DI}
0: {WC_H, WC_I, DI} 

bit[2]: WC Check of MIPI HREF 
0: No check; 1: check 

bit[1]: data_type check 
( Is it raw8 or raw10?) 
0: No check; 1: check 

bit[0]: MIPI ECC check 
0: No check; 1: check
0x12read-writebit[7]: Two Extended IOs as PWM or GPIO
0: GPIO; 1: PWM

bit[1:0]: GPIO Direction
0: CPLD input; 1: CPLD output
0x13read-onlybit[1:0]: GPIO read-in values
0x14read-writebit[1:0]: GPIO write-out values
For example:
If 0x12 writes 0x03, 0x14 writes 0x55, then GPIO is output with a value of 0x03. 

If 0x12 writes 0x01, 0x14 writes 0x01, then GPIO [1] is the input; GPIO [0] is the output, and the value is 0x01.
0x15read-writebit[5:4], Selection of pwm_0 Cycle Counting Clock 

bit[1:0]: Clock selection for pwm_0 high-level counting 
3: 40us
2: 20us
1: 10us
0: 5us
0x16read-writebit[7:0]: Number of High Level Width Clocks in pwm_0
0x17read-writebit[7:0]: Number of pwm_0 Periodic Width Clocks
0x18read-writebit[5:4]: Selection of pwm_1 Cycle Counting Clock 
3: 320us
2: 160us
1: 80us
0: 40us 

bit[1:0]: Clock selection for pwm_1 high-level counting 
3: 40us
2: 20us
1: 10us
0: 5us
0x19read-writebit[7:0]: Number of Clocks with High Level Width in pwm_1
0x1Aread-writebit[7:0]: Number of pwm_1 Periodic Width Clocks
0x1Eread-onlyRead MIPI parsed information 
bit[7:0]: MIPI DATA ID
0x1Fread-onlyRead MIPI parsed information 
bit[4:0]: MIPI, Image resolution, column, High 5 bits
0x20read-onlyRead MIPI parsed information 
bit[7:0]: MIPI, Image resolution, column, Low 7 bits
0x21read-onlyRead MIPI parsed information 
bit[4:0]: MIPI, Image resolution, row, High 5 bits
0x22read-onlyRead MIPI parsed information 
bit[7:0]: MIPI, Image resolution, row, Low 7 bits
7.3 USB and CPLD Configuration6

CPLD is 8-bit address, 8-bit data working mode.

3.2.1 Set frame skip

VRCMD = 0xD7, 0x4600, 0x0400, 1, 0x12

Register 0x04 is used to set the frame skipping function.
When the camera output frame rate is fast and exceeds the USB2.0 transfer bandwidth (USB2.0 bandwidth is about 40MB/s), the CPLD can perform frame skipping processing to reduce the number of uploaded frames to fit the USB2.0 bandwidth without changing the camera configuration.

Take the configuration file OV5647_MIPI_2Lane_RAW8_8b_2592x1944_8fps.cfg as an example

The camera itself outputs 16fps, the camera output bandwidth is 2592 x 1944 x 16/1024/1024 = 76.9MB/s, which exceeds the USB2.0 bandwidth (40MB/s).
If you do not do frame skipping, the camera keeps sending data to the CPLD, and the USB2.0 is too late to take the data, then the CPLD cache will soon be overflowed, resulting in data disorder, and the upper computer will report errors when displaying, and the green LED on the board will become bright.

For example, set 0x04 to 0x00, without frame skipping processing.

VRCMD = 0xD7, 0x4600, 0x0400, 1, 0x00
7.3 USB and CPLD Configuration7
7.3 USB and CPLD Configuration8

In this case, either change the camera configuration (lower PLL, increase HTS or VTS), or reduce the upload bandwidth by dropping some of the frame data through the CPLD frame skipping function.
The meaning of the 0x04 register value is shown below:

7.3 USB and CPLD Configuration9

The value is 0xMN, in general, only M frames are uploaded per N frames; 0x00, 0x01 and 0x11 are special values.

For example, if 0x04 is set to 0x12

VRCMD = 0xD7, 0x4600, 0x0400, 1, 0x12

That only 1 frame is uploaded for every 2 frames, the upload bandwidth becomes 76.9 / 2 = 38.4 MB/s, which is less than the USB2.0 bandwidth (40 MB/s).

Click 【load】to reload the modified configuration, then click 【open】 and 【play】.
The upper computer can output the picture normally, no longer report the error, the bottom left corner shows the current frame rate is 8fps (the camera itself outputs 16fps but it becomes 8fps after the frame skipping).

7.3 USB and CPLD Configuration10


  • The maximum frame skipping can be set to 0x1F, which means that only 1 frame is taken every 15 frames.
  • If the camera itself is not fast and the frame skipping is set too large, it may cause the USB not to receive data for a long time (about one or two seconds), at this time the upper computer can output the picture, but still report an error (USB transfer timeout error).
7.3 USB and CPLD Configuration11

3.2.2 Set MIPI Lane channel and RAW format

VRCMD = 0xD7, 0x4600, 0x0C00, 1, 0x81
7.3 USB and CPLD Configuration12
  • MIPI Lane channels have 1Lane, 2Lane and 4Lane configurations.
  • RAW has two types of RAW8 and RAW10 (other RAW formats are not supported at this time).
Lane channelRAW Format0x0C value


If Lane channel and RAW format are not configured correctly, it will result in the CPLD not being able to parse the MIPI data and the upper computer not being able to output the image.

3.2.3 Set the MIPI resolution reference value

VRCMD = 0xD7, 0x4600, 0x0D00, 1, 0x0A
VRCMD = 0xD7, 0x4600, 0x0E00, 1, 0x20
VRCMD = 0xD7, 0x4600, 0x0F00, 1, 0x07
VRCMD = 0xD7, 0x4600, 0x1000, 1, 0x98

The registers 0x0D to 0x10 are used to set the resolution referenced value. 0x0D to 0x10 is meaningful when the wordcount checksum (bit[2] of register 0x11) is turned on for MIPI resolution.

7.3 USB and CPLD Configuration13
  • If 0x11 is set to 0x03, the wordcount checksum is not turned on, 0x0D ~ 0x10 can be ignored.
  • If 0x11 is set to 0x07, 0x0D ~ 0x0E value must be correct, otherwise HREF can not be parsed out, the upper computer can not output the image.

3.2.4 Set MIPI checksum

VRCMD = 0xD7, 0x4600, 0x1100, 1, 0x07

Register 0x11 is used to set several MIPI checksum methods (DataID, WordCount, ECC).

MIPI data contains DataID, WordCount, and ECC data regardless of whether it is a short packet (indicating field start and field end) or a long packet (indicating a line of data).

7.3 USB and CPLD Configuration14
7.3 USB and CPLD Configuration15

DataID is divided into VC (Virtual Channel) and DT (DataType).

7.3 USB and CPLD Configuration16

VC is generally not used; RAW8 and RAW10 are commonly used by DT.

7.3 USB and CPLD Configuration17
7.3 USB and CPLD Configuration18


If the MIPI checksum is not set or set incorrectly, it may lead to the MIPI data parsing error and can not produce the map.

7.3 USB and CPLD Configuration19
  • bit[0] sets the ECC checksum, which is usualluy set to 1.
  • bit[1] sets the DataType checksum. When set to 1, only MIPI data with RAW8 (DataType=0x2A) or RAW10 (DataType=0x2B) can be parsed.
  • bit[2] sets the WordCount check, MIPI data can only be parsed if the WordCount is the same as the set value of 0x0D~0x0E when bit[2] is set to 1.
  • bit[5:4] sets the order of ECC generation. ECC is generated based on the three bytes DI, WC_H and WC_I, and the ECC values generated by different orders are different.

Most cameras can configure this order, and the default order is usually DI, WC_I, and WC_H.

7.3 USB and CPLD Configuration20

In general.

  • 2Lane or 4Lane only need to enable the ECC check and DataType check, WordCount check could not be enabled. In other words, the 0x11 register is set to 0x03, and it does not matter if the 0x0D to 0x10 registers are not used
VRCMD = 0xD7, 0x4600, 0x1100, 1, 0x03
  • WordCount checksum needs to be enabled at 1Lane, otherwise the parsing may be unstable. In other words, 0x11 register is set to 0x07, at this time, 0x0D~0x10 registers need to be set correctly according to the actual resolution, if the resolution is not set correctly, it will cause HREF not to be resolved, and the upper computer will not be able to output the image.

For example, OV7251 1Lane RAW8 configuration:

7.3 USB and CPLD Configuration21

3.3 Camera Configuration

7.3.3 Camera Configuration1
7.3.3 Camera Configuration2
7.3.3 Camera Configuration3

[register parameter]: Register parameter set for USB2.0 & USB 3.0 mode.
[register parameter][dev2]: Register parameter set for USB2.0 mode.
[register parameter][dev3][inf2]: Register parameter set for USB3.0 mode and USB 2.0 interface.
[register parameter][dev3][inf3]: Register parameter set for USB3.0 mode and USB 3.0 interface.

Only the configurations in [register parameter] and [register parameter][dev2] are valid for the USB 2.0 Camera Shield Rev.E​

For example:

  • REG = 0x3035, 0x11 means the address is 16 bits and the data is 8 bits.
  • The I2C_MODE and I2C_ADDR at the beginning of the configuration file should be set correctly first.
7.3.3 Camera Configuration4

The specific configuration of the camera requires reference to the datasheet.
Commonly used registers such as PLL, VTS/HTS, Exposure, Gain, RAW mode, etc.

7.3.3 Camera Configuration5
7.3.3 Camera Configuration6
7.3.3 Camera Configuration7
7.3.3 Camera Configuration8

4.Modification Examples

The following are a few scenarios for modifying the configuration file for reference.

4.1 Change RAW8 to RAW10

Take the configuration file OV5647_MIPI_2Lane_RAW8_8b_2592x1944_8fps.cfg as an example, now we want to modify it to 2Lane RAW10 2592×1944 configuration, i.e. the number of Lanes and resolution remain the same, just modify the RAW format.

First, make a copy of OV5647_MIPI_2Lane_RAW8_8b_2592x1944_8fps.cfg.

7.4 Modification Examples1

Second, rename the copied file.

7.4 Modification Examples2

Third, open with a text editor (e.g. Notepad++).

Since the camera and resolution are not changed, the [Camera parameter] section does not need to be modified.

7.4 Modification Examples3

In the CPLD configuration, change the 0x0C register value from 0x81 to 0x91.

7.4 Modification Examples4
7.4 Modification Examples5

Check the camera manual and find the register for modifying the RAW format.

7.4 Modification Examples6

The 0x3034 register defines the RAW format. The default value is 0x1A, which means RAW10; if it is 0x18, it means RAW8.

Then look for 0x3034 in the configuration file, and find it in two places, the last one prevailing.

7.4 Modification Examples7

0x3034 current value is 0x18, change it to 0x1A.

Save the modified configuration file.

Click 【refresh】 to see the newly created file only in the drop-down list.

7.4 Modification Examples8

Click 【load】-【open】-【play】 in turn, out normal image.

7.4 Modification Examples9

Click 【Tools】-【Data Info】

7.4 Modification Examples10
7.4 Modification Examples11

It shows that the DataType parsed by the CPLD is 0x2B, which also indicates that it is indeed in RAW10 format.

7.4 Modification Examples12


1.If the upper computer reports badframe error after RAW8 is changed to RAW10, it may be because the amount of data in one line is increased to 1.25 times, and the HTS is too small, so the HTS needs to be increased to output the image.

2.Some cameras also need to modify the PLL register when the RAW format is modified.

3.Because the upper computer cannot parse RAW10 at present, the CPLD on USB2.0 Camera Shield Rev. E is throwing away the lower two bits of 10bit and turning them into 8bit before uploading, so BIT_WIDTH is set to 8bit.

4.2 Fix RAW Format and Resolution

The following is how to correct the profile if the number of Lanes is known, but the RAW format and exact resolution are not known ( assuming that the camera output is normal, just not sure that the USB2 Camera Shield is properly configured).

Still take OV5647_MIPI_2Lane_RAW8_8b_2592x1944_8fps.cfg configuration file as an example.

First, make a copy of OV5647_MIPI_2Lane_RAW8_8b_2592x1944_8fps.cfg, then modify this copy file.

7.4.2 Fix RAW Format and Resolution1

Open with a text editor (e.g. Notepad++).

We intentionally changed the SIZE wrong from 2592,1944 to 2500,1900

7.4.2 Fix RAW Format and Resolution2

Change the 0x0C register to 0x91 from 0x81 by mistake as well.

7.4.2 Fix RAW Format and Resolution3

The upper computer loads this configuration file and the error is reported (Bad frame received).

7.4.2 Fix RAW Format and Resolution4

MIPI Data Info information is also abnormal.

7.4.2 Fix RAW Format and Resolution5

Then, we change the 0x11 register value from 0x07 (or 0x03) to 0x01.

7.4.2 Fix RAW Format and Resolution6

Save, reload, and check the MIPI Data Info.

7.4.2 Fix RAW Format and Resolution7

0x2A indicates RAW8 with a resolution of 2592×1944.

7.4.2 Fix RAW Format and Resolution8

Now fix the configuration file:

  • change the SIZE to 2592,1944.
  • change 0x11 to 0x03.
  • change 0x0C to 0x81.

The image will come out normally.


If the camera output is in RAW10 format, after changing 0x11 to 0x01, the Col value in MIPI Data Info at this time is not the column resolution, but the number of rows (WordCount).
For example, the following figure shows the result after changing 0x11 to 0x01 on the RAW10 configuration.

7.4.2 Fix RAW Format and Resolution9

0x2B means it is RAW10, and the amount of RAW10 data is 1.25 times of RAW8, so the column resolution should be 3240/1.25=2592.

Or fix 0x11 and 0x0C first (change 0x11 to 0x03 and 0x0C to 0x91), then check MIPI Data Info (Col and Row are accurate at this point), and finally fix SIZE.

7.4.2 Fix RAW Format and Resolution10

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